`timescale 1ns / 1ps
`include "defines.vh"
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/06/11 22:24:27
// Design Name: 
// Module Name: IF_ID
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module IF_ID(
    input [0:0] clk,
    input [0:0] rst,

    input [0:0] Clear_Flag_Input,

    input [`Instruction_Bus]Instruction_input,
    input [`Instruction_Addr_Bus]Instruction_Addr_input,


    output [`Instruction_Bus] Instruction_output,
    output [`Instruction_Addr_Bus] Instruction_Addr_output
    );


    Latch #(32) Latch_IF_ID_Instruction(.clk(clk), .rst(rst), .Clear_Flag(Clear_Flag_Input), .Default_Value(`INST_NOP), 
                            .Write_Input(Instruction_input), .Read_Output(Instruction_output));

    Latch #(32) Latch_IF_ID_Instruction_Addr(.clk(clk), .rst(rst), .Clear_Flag(Clear_Flag_Input), .Default_Value(`Zero32), 
    .Write_Input(Instruction_Addr_input), .Read_Output(Instruction_Addr_output));

                 
                           


    always @(posedge clk) begin
        $display($time,"=================  IF_ID:  Instruction:%d",Instruction_output);
    end




endmodule
